RTL Design Engineer Jobs In san francisco, CA

FPGA Engineer

quadric.io, Inc - burlingame, CA

Quadric has created an innovative general purpose neural processing unit (GPNPU) architecture. Quadric's co-optimized software and hardware is ...

Created: 2024-07-07

Sr. Functional Safety Design & Verification Engineer

Red Oak Technologies - berkeley, CA

Red Oak Technologies is a leading provider of comprehensive resourcing solutions across a variety of industries and sectors including IT, ...

Created: 2024-10-17

RTL Design Engineer

Saxon Global - san francisco, CA

Hi Hope you are doing good. We are looking for RTL Design Engineer. This is a contract position. Please check the job description and reply to ...

Created: 2024-09-23

FPGA Engineering Lead

Women Impact Tech - san francisco, CA

Responsibilities: Define, develop, and integrate features across our FPGA stack with a focus on functional safety and reliability. FPGA ...

Created: 2024-09-14

RTL Engineer

Wipro - san francisco, CA

10+ years of experience in RTLVerilog writing.Have expertise in static checking like CDC, Lint, RDC, Spyglass DFT along with module integration ...

Created: 2024-07-07

Senior FPGA Engineer (USG)

Astranis - san francisco, CA

Astranis is on a mission to bridge the digital divide by connecting the four billion people worldwide who currently lack internet access. We're ...

Created: 2024-09-10

Lead FPGA Engineer

Ouster - san francisco, CA

At Ouster, we build sensors and tools for engineers, roboticists, and researchers, so they can make the world safer and more efficient. We've ...

Created: 2024-09-25

Classroom Technology Support Supervisor (7561U) Research, ...

University of California Berkeley - Berkeley, CA

40% - Supervision of RTL Classroom Support and Student Workforce Program Team. Partner with the senior manager for classroom technology services ...

Created: 2024-10-14

Senior Physical Design Engineer

ACL Digital - san francisco, CA

Full chip and Block constraints development and constraints generation. Full chip and Block Synthesis, STA and timing closure using Primetime ...

Created: 2024-07-07

Principal/Senior Staff/Staff GPGPU Design Engineer

Sql Pager LLC - san francisco, CA

Principal/Senior Staff/Staff GPGPU Design Engineer Client Overview Client is building the first latency optimized SoC for their industry. Using ...

Created: 2024-07-07