Firmware/FPGA Verification Engineer - Secret Clearance ...

Job Description:Firmware Engineering and FPGA design responsible for the analysis, design, programming, debugging and modification of software and troubleshooting code for firmware (IC embedded code) applications.Work often involves analog and digital hardware and software operating systems.Performing Design Architecture activities for various programs and IRAD projectsTypically programs in machine language, assembly language and high level languages (e.g., System Verilog, VHDL, C, C ).Working with Hardware Engineering Team to complete Hardware Development, Simulation and Verification for digital signal processing and general processing projectsSupporting Integrated Product Teams, Engineering Project Manager, and Program Office staff to meet all customer objectives and program milestones.Required Experience:-Ability to perform FPGA/Firmware architecture and design-General knowledge of standard test equipment such as oscilloscopes, signal generators, and spectrum analyzersPosition requires knowledge and exposure to hardware design.System Verilog and/or VHDL, C, C , and Matlab experience is RequiredDigital Signal Processing (DSP) experienceLevel 2: BS 4-8 YRS or MS 2-6 YRSWe typically use VHDL, although System Verilog experience is also a plus.Position will require Min two days a week onsite dependent on program requirements for the week.Nesco Resource offers a comprehensive benefits package for our associates, which includes a MEC (Minimum Essential Coverage) plan that encompasses Medical, Vision, Dental, 401K, and EAP (Employee Assistance Program) services.Nesco Resource provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws.

Created: 2025-03-03