Engineer|5287 Engineer|5287

Job Description: Join our Technologies Inc Global CAD team delivering SoC design CAD Tools for leading-edge products. The position requires an experienced CAD development Engineer to develop RTL2GDS implementation tools and flows for new methodologies of PPA and Sign-off in cutting edge process nodes.The CAD team at QCOM is looking for long-term Temp staffing for driving Tools and Flows for upcoming Snapdragon products. Key responsibilities include: Synthesis, Floorplan, Place and Route, Static Timing analysis, IR drop analysis, Physical verification and Logic verification. The Tools and flows are based on EDA vendors Synopsys, Cadence, Mentor, Ansys who deliver EDA tools for Chip design. Synopsys tools include: Fusion Compiler, Design compiler (DC), Formality, Tetramax, PrimeTime, STAR-RC, IC validator. Cadence tools include: Genus, Innovus, Conformal, Tempus, Voltus. Mentor tools include: Aprisa, AtopTech, Tessent, Calibre. Ansys tools include: redhawk, Totem. Experience at EDA vendors or chip companies is a plus. Candidates with titles like CAD engineer, PD engineer, or Synthesis engineer can be trained by the CAD team. Experience in adjacent areas such as Spice simulations, IP design, or memory design is also considered valuable. Automation skills in Tcl, PERL, or Python are beneficial. Overall, our team builds tools and flows for the most complex chips in advanced technologies. We welcome engineers to learn and build the latest tool platforms. This role's responsibilities will include: Develop and support CAD tools and flows for Synthesis, Floorplan, Place and Route, and ECO. Debug issues and provide solutions for design closure in advanced process nodes. Regression, Test, analysis of QoR results and develop recipes for PPA and runtime/compute optimization. Collaboration with design teams and CAD teams. Interfacing with EDA vendors to enable production-ready tool sets that satisfy project requirements. Minimum Qualification Requirements: Hands-on expertise in developing and maintaining CAD tools for digital design. Knowledge of Industry EDA tools and PPA optimization techniques. Strong logical and creative problem-solving skills with excellent analytical and debugging skills. Excellent interpersonal and analytical skills with the ability to work independently. Highly motivated, excellent team spirit, product and customer-oriented. 2-4 years experience. Preferred Qualifications: 3+ years CAD flow development for ASIC design, floorplan, place and route and related work experience. 2+ years of experience in advanced process technology. 2+ years experience with EDA vendor tools. 2+ years hands-on experience with Tcl and Python languages. Education Qualifications: Required: Bachelors in Computer Engineering and/or Computer Science and/or Electrical Engineering with courses on VLSI and/or CAD tools. #J-18808-Ljbffr

Created: 2025-03-01