Senior Hardware Engineer, Physical Design - MTV

Google DeepMind is developing several AI tools. Gemini is a large language model, Veo is a video generation model, Imagen 3 is a text-to-image model. AlphaFold predicts protein structures, and SynthID identifies AI-generated content. These tools demonstrate cutting-edge AI capabilities and are being used for a variety of research and applications. Google DeepMind emphasizes responsible AI development. Benefits: Enhanced maternity, paternity, adoption, and shared parental leave Private medical and dental insurance for yourself and any dependents Flexible working options Healthy food An on-site gym Education Requirements: PhD in a technical field or equivalent practical experience Experience Requirements: Knowledge of the latest in large machine learning research Experience working with simulators and real-world robots Expertise in using large datasets with deep neural networks to make real robots useful A real passion for AI impacting real world robots! Responsibilities: Design, implement and evaluate models and software prototypes of robotic agents. Report and present research findings and developments including status and results clearly and efficiently both internally and externally, verbally and in writing. Suggest and engage in team collaborations to meet ambitious research goals. Work with external collaborators and maintain relationships with relevant research labs and key individuals as appropriate. Safety Responsibilities: Performing Hazard and Risk Analysis for emerging Robotics Platforms. Provide expertise and guidance on Implementing state-of-the-art safety solutions on our robots and workcells, to enable safe data collection and model evaluation. Working closely with Google DeepMind Robotics Researchers to accelerate development of new capabilities while ensuring safety. Coordinating with Environment, Health and Safety (EHS) teams to ensure consistency across GDM Robotics Labs. Senior Hardware Engineer, Physical Design - MTV Experience Requirements: At least 10 years experience in ASIC physical design flows and methodologies in advanced nodes. Experience from PD for high performance compute IPs (e.g., GPUs, DSPs, or machine learning accelerators). Successful track record of delivering tape-outs to production. Capability and strong willingness to work in PD in a research environment. Hands on experience and a solid understanding of ASIC physical design, physical design flows and methodologies including synthesis, place and route, STA, Formal Verification, CDC and Power Analysis using tools such as Design Compiler, FC, Innovus, PrimeTime, PrimeTime-PX, Calibre, ICV, Conformal, RedHawk, Spyglass and PowerArtist. Strong scripting skills in Python, TCL, BASH. Responsibilities: Work in a fast and interdisciplinary team bringing together experts from Machine Learning, Hardware, Programming Languages and Systems. Work in close collaboration with HW architects and design engineers rapidly iterating experimental designs, giving rapid yet reliable feedback on the performance, power and area of different design options. Drive architectural feasibility studies, explore RTL/design tradeoffs for physical design closure. Perform block level physical implementation steps including synthesis, floorplanning, place and route, power/clock distribution, congestion analysis, STA, timing closure, EM-IR, PV, CDC analysis, LEC etc. Provide actionable feedback to silicon design engineers and architects for design improvements. #J-18808-Ljbffr

Created: 2025-03-01