Physical Design Engineer (Sunnyvale, CA)

ResponsibilitiesConsidering applying for this job Do not delay, scroll down and make your application as soon as possible to avoid missing out.Responsible for implementation of ultra-high performance and low power data processing chipWork with RTL designers to achieve PPA goals and suggest appropriate tradeoffsFloor-planning, experimenting with placement and routing techniques for better PPADo timing closure for very high frequency designs with possible hand placement of logic when neededHelp define low latency/low skew clock tree methodology/designHelp define appropriate power grid structures to meet EM/IR goalsScripting and automating flows to improve turn-around timesQualificationsMember of core team responsible for the crafting and timely delivery of PD partitionsStrong communication and interpersonal skills required to work with our global design teamSuccessful track record of mentoring junior engineers and interns a plusMore than 5 years of experience in high performance semiconductor designsVerilog knowledge and an understanding of ASIC design flowExpertise in logic synthesis, prototyping, timing analysis, floor-planningExpertise in flow automation (Perl, Tcl, Python) and understanding of full PD methodologyExperience with Innovus on 7nm or lower technology nodesA background in computer architecture is desirableThe ability to learn new technologies and apply that knowledge quicklyaProven track record demonstrating the ability to meet project milestones and deadlinesBS or MS Degree in Electrical Engineering or Computer ScienceFamiliarity with basic synthesizable RTL designs (flops, fifos Clock domain crossing) is a plus.Strong familiarity with any of these protocols: PCie, Ethernet (100G and above), DDR4.Ability to create regression scripts to run individual and batch jobs on grid.#J-18808-Ljbffr

Created: 2025-01-01