Senior SoC Design & Integration Engineer

Senior SoC Design & Integration Engineer About Xcelerium:Xceleirum is a fabless semiconductor company developing advanced edge processors that bring AI processing to high-bandwidth sensors and wireless devices, unlocking hidden insights from every RF signal.Working at Xcelerium will provide an opportunity to work on a complex development from the ground up and become familiar with cutting edge technologies such as the wireless signal processing, computer vision, sensor fusion, machine learning and the opportunity to create and implement ground-up the latest VLSI methodologies with a collaborative, innovative team. In addition, the application domains will be 5G, UAVsDrone, Robots, and Autonomous Vehicles which provide enormous scope for growth and making an impact.About the JobWe are seeking a Senior SoC RTL Design & Integration Engineer to lead the SoC chip-top RTL design and integration, ensuring smooth and efficient integration of all subsystems, IPs, and hard macros into a complete SoC design. The engineer will be responsible for RTL implementation, synthesis constraints, IO padring design, powerthermal analysis, and physical design collaboration, helping to drive timing closure and system-level optimizations.This role requires deep expertise in SoC architecture, RTL design, synthesis, timing, and physical implementation, as well as experience working across disciplines, including DFT, Physical Design (PD), PowerIR Drop analysis, and Package Integration. The engineer will collaborate closely with the Senior DFT Engineer to ensure seamless DFT integration at the SoC level.ResponsibilitiesSoC RTL Design & Subsystem IntegrationOwn the chip-top RTL design and integration, ensuring seamless functionality across tegrate internal and external IPs, including CPU cores, analog IP, memories, and peripherals.Work closely with subsystem RTL teams to ensure a smooth SoC-level integration.Develop and maintain a modular, scalable, and synthesizable RTL codebase.IO Ring (Padring) & Hard Macro IntegrationDesign and implement the SoC's input-output (IO) ring (padring).Ensure proper integration of hard macros, including PLLs, PMUs, SRAMs, and PHYs.Define ESD protection and power domain partitioning strategies at the SoC level.Timing, Synthesis, and Physical Design CollaborationDefine and validate timing constraints (SDC) and synthesis constraints for the SoC.Work with the Physical Design (PD) team on SoC-level floorplanning, placement, and routing.Drive timing closure efforts, ensuring SoC-level clock domain crossings (CDC) and reset strategies are robust.Power, Thermal, and IR Drop AnalysisCollaborate with PD teams to optimize power distribution networks (PDN) and minimize IR drop issues.Ensure SoC meets thermal design power (TDP) constraints and package thermal limits.Work with package engineers to address package design, parasitic noise, crosstalk, and electromagnetic interference (EMI).Collaboration with DFT & Test EngineeringWork closely with the Senior DFT Engineer to seamlessly integrate scan chains, BIST controllers, and JTAG structures at the SoC level.Ensure SoC design-for-testability (DFT) readiness, including boundary scan, scan compression, and ATPG pattern validation.Support post-silicon validation and debugging efforts in collaboration with test engineering teams.Qualifications8+ years of experience in SoC RTL design, integration, and implementation.Strong expertise in SystemVerilog and HDL-based RTL design for complex SoCs.Experience in chip-level integration, including IPs, hard macros, and analogdigital interfaces.Solid knowledge of clocking architectures, CDC, and reset domain crossings (RDC).Hands-on experience with timing constraints (SDC), STA, and timing closure.Experience working with EDA tools:Synthesis: Synopsys Design Compiler, Cadence Genus, or equivalent.Timing Analysis: PrimeTime, Tempus, or equivalent.Physical Implementation Collaboration: Floorplanning and powerthermal analysis.Understanding of PDN design, IR drop, power integrity, and package constraints.Familiarity with DFT methodologies, including scan, BIST, and ATPG integration.Strong problem-solving skills and the ability to work in a cross-functional engineering team.Bachelor'sMaster'sPhD in Electrical Engineering, Computer Engineering, or a related fieldCompensation And BenefitsWe provide competitive compensation and benefits

Created: 2025-03-08