PER International | Memory Architect

Our Client is one of the world's largest global Top-tier Semiconductor Company. Their chips are used by some of the biggest names in the tech industry, and they are helping to shape the future of technology - thus, making them a major force in the semiconductor industry.The ideal candidate will join the Memory System Design Team, working with architecture, modeling, silicon, software, and other design teams to develop a competitive design. We are searching for someone hands-on and experienced with memory performance improvement to benefit memory access behavior in sophisticated system.Role Location: San Jose or San Diego, CaliforniaJob Description:Drive Memory System architecture and designs to optimize power, performance, and implementationShow system-level understanding of performance trade-offs, system architecture, memory subsystems, and various memory technologies (DDR3, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR5 etc.)Develop and implement tailored Memory Systems. Validate functionality, improve design revisions, and meet performance targets as well as system requirements.Experience in computer architecture, microarchitecture, and performanceDesign experience and knowledge in architecture, RTL design, performance analysis, and power optimization.Experience in designing and optimizing system-level cacheExperience with DRAM interface standards and memory technologies such as DDR3, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR5 etc.Familiarity with system cache, memory controller or DDRPHY for safety, securityFamiliarity with the architecture and the micro-architectures of recent ARM processor is a plusFamiliarity with AMBA AXI, CHI, and LPDDR45 interfacesprotocols is a plusINTERESTED?We are committed to submitting suitable candidates for this vacancy to our client ASAP, for more information contact Renz Moreno at PER Recruitment or send your CV to

Created: 2025-01-14