ACL Digital | Failure Analysis Engineer

Job Title: Failure Analysis Engineer, Senior Location: San Diego, CA (100% Onsite) Duration: Contract Project Job Description: Top 5 Required Skills: 1. Microelectronics background (electrical engineering degree) 2. Hands on able to work in lab bench equipment 3. Trouble shooting - systematically diagnosing fail signature by correlating electrical test data from multiple sources and fault isolation. 4. Strong Written and Verbal communication with ability to tailor message to audience (FinanceMarketing, engineering, end customer, etc). 5. Ability to work independently or in team environment. Flexible work environment. (professional examples preferred cross-functional team). (Behavioral examples: Team sports, playing in bands, etc.) Technologies: Basic transistor characterization for Digital and RF microelectronics. Education Requirement: Bachelor's degree or equivalent in Science, Engineering, or related field and 2+ years of chip or wafer-level Failure Analysis (e.g., physicalelectrical failure analysis) or related work experience. . OR Master's degree in Science, Engineering, or related field and 1+ year of chip or wafer-level Failure Analysis (e.g., physicalelectrical failure analysis) or related work experience. Years of Experience Requirement: • 2+ year of working experience in a physicalchemical laboratory setting. Preferred Qualifications: • 3+ years of chip or wafer-level Failure Analysis (e.g., physical failure analysis, electrical microscopy, nanoprobing) experience or related work experience • Applies knowledge of failure analysis (e.g., physicalelectrical failure analysis, etc.) to determine the cause of failure by evaluating electrical and mechanical characteristics of systems andor integrated circuits, components, and sub-components. • Administers non-destructive testing on devices using imaging tools (e.g., X-ray, C-SAM) andor optical inspections. • Performs failure analyses on issues (e.g., level 2) requiring creative problem solving. • Performs physical failure analyses by examining individual layers of silicon to reveal evidence of defect; contributes to high-risk, isolated issues in which analysis can only be performed once on a single device.

Created: 2025-01-14