Noblesoft Technologies | Design Verification Engineer
Noblesoft Technologies - san jose, CA
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Role : Design Verification EngineerLocation : San Jose CA (Onsite)Responsibilities:â— Develop verification methodology and testbenches for digital and mixed-signal blocksâ— Test plan, coverage analysis and closure for parallel link and SerDes IP blocks and on-chip interconnectsBasic Qualifications:â— BS, MS in Electrical Engineering, Computer Engineering, or related fieldsâ— Experience:â—‹ Local US lead is expected to have 10+ years of work experience in ASIC design verificationâ—‹ Other engineers expected to have 2 to 5 years of work or academic experience in ASIC design verificationâ— History of assuming responsibility for a variety of technical tasks and completing projects independentlyâ— Proficient in System Verilog, UVM testbench development for design verification of complex digital and PHY blocks (in AMS and WREAL modeling verification)â— Proficient in pre-synthesis, and post- place-and-route functional verification (NCSIM, VCS, ModelSim)â— Proficient in scripting or programming languagesâ— Experience working with version control software, such as GitPreferred Qualifications:â— Experience working on digital designs with multiple clock domains and clock dividersâ— Experience in verification of SerDes IP block interfaces in a complex SoC fabric environmentâ— Experience in verification of the PCS, PMA SerDes layers and internal SerDes digital backendsâ— Experience with verification of HBM memory interfaces (PHY and controller)â— Experience in formal model equivalence checking tools and verification methodologyâ— Programming experience in Python
Created: 2025-01-01