DFT Engineer - All levels

DFT Engineer - all levels.THIS IS NOT AN ENTRY LEVEL ROLE - PLEASE NO RECENT GRADUATESA RISC-V start up is looking for DFT Engineers of all levels. We have roles for all levels from Engineer to Senior and through to LeadManager positions.The positions are available across Mountain View CA , Austin TX, Portland OR, Fort Collins COWe have open positions for full-time roles in DFT design, ranging from unit level to chip level, encompassing various aspects of DFT design functions such as scan, MBIST, and ATPG.Opportunities exist in both CPU and SOC DFT design and verification.Responsibilities:Develop DFT strategy and methodologiesDesign DFT featuresDefine test structures, debug structures, and test plansOversee or create test vectorsCollaborate with the physical design team to meet requirementsValidate adherence to DFT requirementsWork with designers to enhance test coverage, debug observability, and flexibilityVerify post-PD designs against DFT requirementsCollaborate with verification engineers and step in to run tests when neededRequirements:Solid understanding of digital logic design, microprocessor, debug features, DFT architecture, CPU architecture, and microarchitectureFamiliarity with DFT and structural debug concepts and methodologies, including JTAG, IEEE1500, MBIST, scan dump, and memory dumpProficiency in Verilog, experience with simulators, and waveform debugging toolsKnowledge of VerilogSystemVerilogFamiliarity with Python, Shell scripting, Makefiles, and TCL (a plus)Strong problem-solving skills, effective written and verbal communication, excellent organization, and high self-motivationAbility to thrive in a team and deliver under aggressive schedulesEducation and Experience:PhD, Master's Degree, or Bachelor's Degree in a technical subject area

Created: 2024-11-09