Performance Architect (Silicon Engineering)

Microsoft ships tens of millions of hardware products every year, including the Xbox, Surface devices, HoloLens, accessories, and much more. Microsoft's silicon development teams incubate advanced technologies and build deep partnerships with internal research, product planning, business, and marketing teams. Opportunities within our silicon teams represent a variety of disciplines including, but not limited to, architecture, design, verification, performance modeling, and physical design supporting the development of custom silicon. We are looking for you to bring your authentic self to help us in designing for the future! As the Performance Architect (Silicon Engineering) , you will work in the team responsible for System On Chip (SOC) / Intellectual Property (IP) performance modeling, including projections, architectural and what-if analysis and direction setting for our programs. You will work closely with the product architecture System On Chip (SOC) architecture teams, IP architecture, to ensure our SOC and IPs enable performant, efficient, and industry-leading systems. The team you'll be part of will be involved in numerous projects within Microsoft, developing custom silicon for a diverse set of systems. We are responsible for delivering cutting-edge, custom SoC designs that can perform complex and high-performance functions in the most efficient manner. Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond. In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positively impact our culture every day. Responsibilities Developing performance modeling methodologies by creating and owning System on Chip (SOC) / Intellectual Property (IP) cycle-accurate/approximate performance models and analysis tools in C++ and Python. Using workload information and working with Micro-architects and Register Transfer Level (RTL) team to identify performance bottlenecks. Collaborate across functionally to propose architectural/microarchitectural changes and provide the required quantitative justification. Verifying the correlation of the SOC performance models to the RTL implementation. Collaborating across teams to come up with the best solution possible with a One Microsoft mindset. Challenging the status quo with a growth mindset to push the envelope and enable world-class SOC products across Microsoft. Embody our culture ( and values. ( Qualifications Required Qualifications: 7+ years of related technical engineering experience OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field. Other Requirements Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter. Preferred Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience or internship experience OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience or internship experience OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ years technical engineering experience. Deep understanding of computer architecture, System on Chip (SOC) and system-software architectures, and their performance tradeoffs. Experience developing SOC performance modeling techniques and benchmarks from conception to microarchitecture specification. Significant understanding of input/output (I/O), memory subsystems, coherency flows, interconnect, Quality of Service (QoS) traffic. Knowledge of performance monitors and post-silicon SOC and performance tuning is a plus. Solid communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams. Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $117,200 - $229,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $153,600 - $250,200 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: Microsoft will accept applications for the role until November 5, 2024. #ahsi #SHPE24MSFT #SCHIE Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations ( .

Created: 2024-11-05