DFT Engineer
ACL Digital - san jose, CA
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Job Title: DFT Engineer Location: San Jose, CA (Hybrid)Duration: Contract Project Job Description: Responsibilities:â— Develop and optimize DFT features for use in complex digital systemsâ— Perform structural scan and at-speed scan insertion, automatic pattern generation, and scancoverage analysis (Cadence Genus w Modus or Siemens Tessent)â— Create DFT patterns for ATE to enable high volume manufacturingâ— Design and contribute to design for test (DFT) methodologiesâ— Work with designers to integrate DFT flow into a digital tool flowBasic Qualifications:â— BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related fieldsâ— Experience:â—‹ Local US lead is expected to have 5+ years of work experience in DFTâ—‹ Other engineer expected to have 1 - 2 years of work or academic experience in DFTâ— History of assuming responsibility for a variety of technical tasks and completing projectsindependentlyâ— Proficient in Verilog for both RTL design and verificationâ— Proficient in structural scan and at-speed scan design, pattern generationverification and BISTmethodsâ— Proficient in ASIC DFT insertion (Cadence Genus, Cadence Modus, Siemens Tessent), andverification (NCSIM, VCS, ModelSim) toolsâ— Proficient in writing timing constraints and deep understanding of timing analysisâ— Proficient in scripting or programming languagesâ— Experience working with version control software, such as GitPreferred Qualifications:â— Working knowledge of architecting DFT features for ASIC and custom blocks in a digital-top flowâ— Experience designing DFT methodologies and flows such as scan insertion, BIST, ATPG, etc.â— Experience working on digital designs with multiple clock domains and clock dividersâ— Performed silicon bring-up, debug, and evaluationâ— Programming experience in Pythonâ— Knowledge of high-speed SerDes or SerDes components
Created: 2024-11-05