Principal Design for Test Engineer

Microsoft's hardware teams incubate advanced technologies and build deep partnerships with internal research, product planning, business, and marketing teams. Microsoft ships tens of millions of hardware products every year, including the Xbox, Surface devices, HoloLens, accessories, and much more. Our opportunities represent a variety of disciplines including, but not limited to, design, verification, performance modeling, and DevOps supporting the development of custom silicon! We are looking for a Principal Design for Test Engineer to join us in designing for the future!"¯ Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond. In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positively impact our culture every day. Responsibilities As a Principal Design for Test Engineer in the Silicon Engineering and Solutions team, you will drive DFT solutions for the product and be at the center of chip design and enabling effort all the way from defining architecture, helping with implementation, ensuring verification coverage and finally with silicon bring-up and validation, for our projects. This will involve numerous projects within Microsoft developing custom silicon for a diverse set of systems."¯ We are responsible for delivering cutting-edge, custom SoC designs that can perform complex and high-performance functions in the most efficient manner."¯ In this high impact & highly visible role on the team, you will be responsible for: Lead the design and implementation of test strategies for multi-chiplet System on Chip(SoC) architectures. Develop and validate test plans, test cases, and test environments for chiplet-based systems. Collaborate with cross-functional teams to define chiplet specifications and integration requirements. Implement Design-for-Test (DfT) techniques to enhance testability and fault coverage. Conduct pre-silicon verification and post-silicon validation of multi-chiplet SoCs. Analyze test data and debug issues to ensure high-quality product delivery. Stay updated with the latest industry trends and advancements in multi-chiplet and SoC design. Design and develop scan insertion and memory BIST (built in self test) insertion, and test the silicon, debug and validate the DFT features on the Automated Test Equipment(ATE). Improve the design, development, and overall quality of the hardware products and development processes. Work on memory BIST design optimization to make sure the design is time, power, and area efficient. Collaborate on a regular basis with memory unit owners for DFT architecture and flow development. Develop methodology and flows for verification and debugging as well as anticipate and avoid blocking issues on projects. Develop ATE test patterns and algorithms to cover various memory and scan fault models. Work on infrastructure and test flow development for unit level and full chip verification. Proactively identify new tools, technologies, and methods to do the job, and understand customer issues for DFT and BIST insertion. Analyze and compare different tools and methods and compare parameters such as area overhead, timing to optimize the DFT solution for the project. Evaluate cost of DFT in terms of die are and test time, cost of memory diagnostics, and benefit of yield recovery for logic and memory redundancy. Justify and show Return on Investment(ROI) for BIST and logic redundancy. Measure repair rates of each chip and identify outlier memory designs that perhaps need circuit work or manufacturing improvement. Other Embody our Culture ( and Values ( "¯ Qualifications Required Qualifications: 9+ years of related technical engineering experience OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience. Minimum 5 years of experience in SoC design and test, with a focus on multi-chiplet architectures. Experience with high-performance computing or Artificial Intelligence(AI) accelerators. Familiarity with advanced packaging technologies (2.5D/3D integration) and understanding of inter-chiplet communication protocols and interfaces. Other requirements: Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Preferred Qualifications: Master or Bachelor degree in Electrical Engineering, Computer Engineering, or Computer Science or equivalent with related engineering experience is required. 15+ years demonstrated experience in DFT for Very Large Scale Integration(VLSI) designs. Effective debug skills for Register Transfer Level(RTL) and gate level simulations. Experience in DFT scan insertion and or Custom Memory BIST design and verification. Ability to work independently and in a team setting and be able to research innovative solutions for challenging business/technical problems. Good technical aptitude and problem solving skills, take initiative, and should be result driven good debugging skills. Familiar with Tessent DFT tools from Mentor Siemens. Well-versed in scan insertion, Automatic Test Pattern Generation(ATPG), Memory Built-In Self-Test(MBIST), Joint Test Action Group(JTAG), Input/Output Built-In Self-Test(IO BIST), Scan Compression, and at-speed testing. Experience with industry standard simulation, ATPG and MBIST tools, particularly Mentor. Knowledge of defect types, fault models, silicon bring-up, debug and validation of DFT features on ATE. Experience with 3rd party High-Speed Input/Output(HSIO) DFT and verification of Serializer/Deserializer(SERDES) is a plus. Good communication and analytical skills. Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $137,600 - $267,000 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $180,400 - $294,000 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: Microsoft will accept applications for the role until October 28, 2024 Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations ( .

Created: 2024-10-19