Principal Design Engineer
XConn Technologies Holdings Inc. - san jose, CA
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Xconn-technologies Inc is a Silicon Valley based company working on the world's leading edge PCIe & CXL Switch for AI/ML & Data center applications. Xconn-technologies is seeking a highly motivated & Passionate Principal design engineer to lead a PCIe/CXL switch subsystem design. Job Description: As a Principal ASIC design engineer, you will lead a part of innovative & advanced design of PCIe & CXL switches for HPC, AI/ML & Data centers. Your primary job is to work closely with architecture team to write micro-architecture specifications from an architecture spec. The job also includes RTL design & helping the design verification test plan as well as preparing design constraints. It is expected to run Lint & Synthesis to ensure RTL quality. Once RTL is complete, you will be supporting the physical design timing closure & assisting the verification team to debug the design. Responsibilities: Participate in architecture definition and modeling. Contribute to micro-architecture specification and reviews. Review industry standard specs and ensure IPs are kept up to date for compliance. Define design partitioning for efficient IP/sub-system/full chip implementation. Review and provide feedback on verification plans and methodology. Drive block/chip/system level development and execution. Work with Hard IP designers, verification, validation, Firmware engineers and architects to produce thoroughly verified, robust IP. Actively participate in post-silicon bring-up, validation and compliance testing. Requirements: 10+ years of experience in logic design using Verilog/System Verilog Proven track record of taking several chips in from product definition to production. Experience in complex & high gate count ASIC design. Experience in PCIe or Ethernet switch or PCIe, CXL controller development is a big plus Good understanding of ASIC design and verification methodologies and flows. Architecture/Micro-architecture definition Design partitioning and Hard IP integration & interactions Multiple async clock domain designs Experience with Clock/Reset trees, & DFT Excellent understanding of Synthesis, STA, CDC, Lint, LEC Familiarity with the peripheral protocols such as UART, I2C, SPI Flash Proficient in Perl scripting
Created: 2024-10-12