Design Verification Engineer
Apolis - mountain view, CA
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Title: Design Verification EngineerLocation: Mountain View, California Experience: 10+ YearsNote: Team is seeking a Design Verification candidate with Strong PCIe expertise along-with complex SoC debug is must. What You'll Be Doing:At-least 10+ years of experience in System Verilog HVL and CC++.At least 10+ year of experience in SVUVM.PortingTesting in FPGA & Emulation (Zebu) Hardware realization Platform is good to haveWhat We Are Looking For:Experience in complete verification cycle which includes development of test plan, BFMDriverMonitorScoreboard component development and integration in test bench, stresscorner testing, failure debug, gate level simulations, assertions, and coverage closure.Verification closure with teamMakePerlPython Ensure customer satisfaction.Reporting to customers on daily or weekly progress effectively
Created: 2024-10-04