DFT Lead

Verilog, Tessent, GenusResponsibilities:Develop and optimize DFT features for use in complex digital systemsPerform structural scan and at-speed scan insertion, automatic pattern generation, and scancoverage analysis (Cadence Genus w Modus or Siemens Tessent)Create DFT patterns for ATE to enable high volume manufacturingDesign and contribute to design for test (DFT) methodologiesWork with designers to integrate DFT flow into a digital tool flowBasic Qualifications:BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related fieldsExperience:Lead is expected to have 5+ years of work experience in DFTHistory of assuming responsibility for a variety of technical tasks and completing projects independentlyProficient in Verilog for both RTL design and verificationProficient in structural scan and at-speed scan design, pattern generationverification and BIST methodsProficient in ASIC DFT insertion (Cadence Genus, Cadence Modus, Siemens Tessent), and verification (NCSIM, VCS, ModelSim) toolsProficient in writing timing constraints and deep understanding of timing analysisProficient in scripting or programming languagesExperience working with version control software, such as GitPreferred Qualifications:Working knowledge of architecting DFT features for ASIC and custom blocks in a digital-top flowExperience designing DFT methodologies and flows such as scan insertion, BIST, ATPG, etc.Experience working on digital designs with multiple clock domains and clock dividersPerformed silicon bring-up, debug, and evaluationProgramming experience in PythonKnowledge of high-speed SerDes or SerDes components

Created: 2024-10-19