Integrated Circuit (IC) Layout and Mask Design Engineer

Select how often (in days) to receive an alert: JOIN OUR TALENT NETWORK Integrated Circuit (IC) Layout and Mask Design Engineer Apply now Date: Sep 11, 2024 Location: Lexington, MA, US Company: MIT Lincoln Laboratory MIT Lincoln Laboratory's Advanced Technology Division develops advanced materials, devices, and subsystems that have broad impact on U.S. Government, industry, and academia. The Division has made a wide range of important contributions during the Laboratory's 70+ year history, including development of bulk and epitaxial crystal growth, charge-coupled device (CCD) imagers, 193-nm lithography, fully depleted silicon-on-insulator (FDSOI) CMOS electronics, semiconductor diode lasers and amplifiers, superconducting electronics and quantum bit (qubit) devices, and photonic integrated circuits (PICs). To enable this advanced technology development, the Laboratory has implemented vertically integrated in-house resources to facilitate design, lithographic mask layout, material growth and characterization, fabrication (e.g., silicon, compound-semiconductor, wafer bonding, flip-chip hybrid), packaging, and testing of electronic and photonic circuits. These in-house resources are used to fabricate a variety of devices and circuits including lasers, waveguide photodetectors, optical modulators, and CMOS and cryogenic electronics with applications in quantum computing, atomic systems, advanced laser sources, microwave photonics, communications, sensing, and other areas of interest to the U.S. Government, industry, and academia. Fabrication resources include: * Microelectronics Laboratory (ML): Cleanroom housing a silicon-fabrication toolset operating on 200-mm-diameter wafers at a 90-nm lithography node, which represents the most advanced silicon fab in the U.S. Government lab system. * Compound Semiconductor Laboratory (CSL): Facilities housing III-V and non-silicon material growth (molecular beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), diamond chemical vapor deposition (CVD)) and fabrication * Microsystems Integration Facility (MIF): Packaging and integration facilities for wire-bonding, vacuum-reflow soldering, flip-chip hybrid integration Job Description The candidate will work as a member of a multi-disciplinary team responsible for the design and layout of lithographic masks for silicon-based, compound-semiconductor, and heterogeneous/hybrid fabrication processes, especially those for photonic integrated circuits (PICs). The candidate may also work on masks for superconducting qubit and trapped-ion qubit quantum computing, radiation-hard CMOS, and other emerging integrated circuit technologies. The engineer will work in the Cadence environment, with which they should be fluent, and will have responsibility for the full layout project from basic layout cell creation to final tapeout. Key tasks will include coding layout pcells; and laying out devices, test structures, systems, and full mask reticles based on input from device and process designers. They will also be responsible for working with the layout team to update and maintain a device pcell library. Required Qualifications * There is no degree requirement for this position * Experience (> 5 years) with design and layout of lithographic masks used for the fabrication of electronic and/or photonic integrated circuits including: o The creation of custom layout blocks and performing layout floor-planning o Design and layout of lithographic masks from devices and test structures to full mask reticles * Ability to work independently with minimal supervision and collaboratively as part of a dynamic, multi-disciplinary team * Excellent organization and intra- and interdisciplinary communication skills * Ability to obtain and maintain a government security clearance Preferred Qualifications: * Bachelor's or Master's degree in electrical engineering, computer science, materials science, physics, chemistry, or a related field * Experience with photonic integrated circuit layout a major plus * Experience with or knowledge of one or more of the following areas: o Using verification runsets, (ideally with Calibre SVRF or Cadence PVS) o The Advanced-Node version of Cadence o Cadence CurvyCore o Programming in Perl, TCL, or Python o Experience with RF layout design At MIT Lincoln Laboratory, our exceptional career opportunities include many outstanding benefits to help you stay healthy, feel supported, and enjoy a fulfilling work-life balance. Benefits offered to employees include: Comprehensive health, dental, and vision plans MIT-funded pension Matching 401K Paid leave (including vacation, sick, parental, military, etc.) Tuition reimbursement and continuing education programs Mentorship programs A range of work-life balance options ... and much more! Please visit our Benefits page for more information. As an employee of MIT, you can also take advantage ofother voluntary benefits, discounts and perks. Selected candidate will be subject to a pre-employment background investigation and must be able to obtain and maintain a Secret level DoD security clearance. MIT Lincoln Laboratory is an Equal Employment Opportunity (EEO) employer. All qualified applicants will receive consideration for employment and will not be discriminated against on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, age, veteran status, disability status, or genetic information; U.S. citizenship is required. Requisition ID: 41417 Nearest Major Market: Boston Job Segment: Facilities, Electronics Engineer, Security Clearance, Chemical Research, Design Engineer, Operations, Engineering, Government Apply now Find similar jobs: Engineering, Advanced Technology

Created: 2024-11-02