Senior DFT Engineer

Job DescriptionResponsible for Design for Test (DFT) of high performance (>1GHz) CPU subsystems using latest DFT methodologies/techniques. Define and implement DFT architecture to enable all the test coverage goals are met. Responsible for generating test pattern and simulating them in Gate Level simulations. Generate and debug failing patterns on Silicon.Required Skills4+ Years of hands on experience in Design for Test (DFT) of high speed (>1GHz) Complex IP, CPU Subsystems and/or SoCExperienced in latest DFT methodologies for High Speed (>1GHz) designs : Scan insertion, Scan compression, ATPG pattern generation, At-Speed testingExperienced in defining and deploying DFT architecture for complex designs preferably CPU subsystems or SoCs to meet the test coverage goalsExpert at using industry standard DFT tools, preferably Synopsys DFT compiler and TetramaxProven Ability to simulate and debug DFT patterns using Gate Level Simulations (GLS)Experience in running and debugging DFT patterns during Silicon BringupExcellent communication skills and ability to communicate and work with other world-wide sitesPreferred SkillsExperience with Memory BIST (MBIST) and Logic BISTProven ability to develop and deploy new DFT methodologies.Strong scripting skills using Perl or TclKnowledge of JTAG

Created: 2025-02-20