Design For Test

DFT for ASIC & SOC IP- FULL-TIME- SAN JOSE- Direct Hire.Senior Or Principal Titles-Key Responsibilities:Implement and verify DFT methodologies specifically for ASIC SoC IP Design.Collaborate with design and architecture teams to identify and define critical testability requirements.Utilize advanced simulation tools and methodologies to thoroughly verify DFT implementations.Analyze DFT-related data and provide insights for continuous design improvements.Document verification processes, results, and best practices to enhance team knowledge and efficiency.Stay updated with the latest trends and technologies in DFT, HBM, and SerDes to drive innovation within the team.Working closely with STA and DI Engineers design closure for testGenerating, Verifying & Debugging Test vectors before tape release.Validating & Debugging Test vectors on ATE during the silicon bring up phaseAssisting with silicon failure analysis, diagnostics & yield improvement effortsInterfacing with the customers, physical design and test engineering/manufacturing teams located globallyWorking closely with I/P DFT engineers & other stakeholdersDebugging customer returned parts on the ATEInnovating newer DFT solutions to solve testability problems in 3nm IPs & beyondAutomating DFT & Test Vector Generation flows. Skills/Experience: Strong DFT background.Proven experience in DFT verification, particularly with HBM, DDR, PCIE and other SerDes IPs.Understanding of DFT methodologies, including scan, BIST, and ATPG.Proficiency in simulation tools and scripting languages (e.g., Perl, Python, TCL and ruby).Solid knowledge in analog and digital circuit design, and device physics fundamentalsExcellent problem solving, debug , root cause analysis and communication skillsExperience working on ATE is a plus.Familiarity with BIST logic for array and link testing is a plus.Knowledge of AHB/APB/AXI buses is a plus

Created: 2025-01-31