Principal Design Engineer - Protium Prototyping ...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.The Cadence AdvantageThe opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.Cadence's employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.The unique "One Cadence - One Team" culture promotes collaboration within and across teams to ensure customer successMultiple avenues of learning and development available for employees to explore as per their specific requirement and interestsYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other"”every day.Job ResponsibilityProtium is leading product in FPGA Emulation/Prototyping domain. This role is to design, verification, timing closure and hardware validation of the FPGA IPs.Developing field-programmable gate array intellectual properties (FPGA IPs) for Protium platform, including design, verification, integration, timing closure, documentation and releasing the IPs to end users;Working on FPGA IP Design, Verification/Simulation, Timing closure, Validation of IP on the hardware;Enhancing current IPs as well as developing new IPs.Debug and fix internal regression failures for FPGA IPs.Documentation of IPsPosition Requirements/Qualifications:BS degree in Electrical Engineering with a minimum of 7 years of experience OR MS with a minimum of 5 years of experience OR PhD with a minimum of 1 year of experienceExperience with FPGA design and verification using VerilogExperience with high end Xilinx(AMD) FPGAs including using Vivado tool for simulation, Place and routeExperience in debugging FPGAs in the lab using Vivado hardware manager, debugging with firmware/softwareExperience using Linux servers, Script development using Shell/Perl/TCLExperience using Cadence Simulators Incisive or XceliumDetailed knowledge about industry standard interfaces such as PCI Express, DRAM/DDR4, SRAM, I2C, JTAG, AXI

Created: 2025-01-24