Senior Package Substrate Design Engineer

The Package substrate design focuses on signal and power integrities analyses as well as routing analyses.This position requires a broad knowledge of package technology and design. Successful candidates will have a deep understanding and experience in the following areas: high performance build-up substrates, flip chip assembly or 2.5D packaging.Knowledge and experience in extracting/simulating package designs for Signal and Power integrities using tools such as HFSS, and/or ADS tools.EducationBachelor's degree in Electrical Engineering, or other semiconductor packaging related discipline - MS is preferred8 to 10 years of experience in semiconductor packaging design, modeling, and simulationsGood experience with signal and power integrity tools (SI/PI tools) for package level extraction/simulationAbility to work with Package Layout engineersStrong presentation and communication skillsPreferredHands on package design; high-speed SI and PI, die and package decoupling caps optimizations, package and PCB SI and PI Characterizations, impedance verification, high frequency s-parameters extraction, Hspice model, package Hspice and RLC model extraction and designsHands on high-speed package and PCB design: high-speed Serdes 112 Gbps, PCIeX5 and 6, LPDDR4,5, Ethernet 25 GBps, power aware SI/PI analysis, up to 40 GHZ s-parameters extraction and verificationPackaging high-speed interconnections timing analyses, eye-diagram and jitter budgeting calculation following the LPDDR JEDEC spec, or other highs-speed frequency domain s-parameters extraction following the base Spec of high-speed interconnectHands on PCB design; SI, PI analyses, decoupling caps optimizations, SI and PI Characterization and extractions, impedance verification, s-parameters verifications with lab measurements, Hspice model, PCB RLC model extraction and designsRouting analyst, chip bumps analyses and package ball analysesPackage material characterization frequency dependent model; skin effects, smoothness, roughness, dielectric loss and dielectric constantPCB material characterization frequency dependent; routing degree of freedomTime domain analyses and jitter budgeting for PCIe2/3/4/5, Serdes 112 GBps, Ethernet 25 Gbps, LPDDR4/5X MIPI, high-speed frequency signalingTime domain analyses and budgeting model for LPDDR 3/4/5, LPDDRX 3/4/5/6Bathtub curve and BER analyses of high speed signalingDDR frequency and time domains model and jitter analyses and path findings to improve package and PCB layout and improve high-speed interconnectionsClock jitter analyses, routing, clock tree analysesSimulating multi-physics electro-thermal analysisCollateral packaging manufacturing and assembly rulesChip and package Reliability analysesDie+Pkg+pcb PDN model time and frequency, Impedance profile, AC droop, DC drop DC, etc.IR drop, and CPM (chip power model) die model using Redhawk and other tolls

Created: 2025-01-14