Analog IC Design Engineer

Pays Up to $150,000 Annually Base Salary Required Skills and Experience BSEE and 8 years' experience required, or MSEE and 6 years, or PhD and 3 years. MSEE preferredDemonstrated Analog IC design experience using SOI CMOSProficient with Cadence tools and solid understanding of general analog circuits such as bias, bandgap, LDO, opamp, charge pump, temperature sensor and etcExperienced in implementing on-chip ESD protection strategies for HBM/MM/CDM on ICStrong understanding of silicon fabrication and how it affects the device physics, device model, and circuit performanceDemonstrated experience debugging, resolving and applying techniques to mitigate analog signal noise coupling and optimum layout for performance, and die size trade offLayout experience using Cadence flow, including LVS and DRC. Ability to work with CAD engineers and provide guidance on analog layoutsGood understanding of MIPI standardGood communication and presentation skillsNice to Have Skills and ExperienceJob Description -Circuit architecture, planning, design, simulation, verification, and production ramp support of highly integrated, high-volume ICs for high-growth, fast-paced, and competitive wireless handset marketKnowledge of RF area circuit experience a plus-Familiarity with cellular standards will be usefulGood understanding of semiconductor physics and strong circuit intuition/simulation skills utilizing Cadence is necessaryPays Up to $150,000 Annually Base Salary

Created: 2025-01-14