Principal Layout Engineer

Locations are San Jose, CA; Richardson, TX; and Chandler, AZResponsibilities:Layout of Power and Analog integrated circuits for the general power electronics market (mobile, industrial, consumer)Floor planning and concept realization of highly integrated analog/power circuitsTop Level and block level layout designs including circuit and layout verification checks (LVS, DRC)Full Analogue layout design and layout size optimization of CMOS JI and SOIInterface and cooperation with Analog and Power IC design engineers in asia and USResponsibility for tape out process, data documentation and data archivingIndependent interface with design engineering, foundry and manufacturingQualifications:10+ years of relevant work experience, 15+ preferredBackground in analog power IC fundamentals and experience with integrated analog mixed-signal circuit layoutsUnderstanding of semiconductor process technologies like CMOS, BICMOS JI, and SOIProven designs in DC-DC converters, including bucks, boosts, and charge pumpsExperience working with voltages in 10-60V range.Experience leading layout design teamsExperience with CAD layout tools like CadenceFluent in Vietnamese. (Only for San Jose location)Outstanding Analytical and problem-solving skills

Created: 2025-01-07