Principal Memory Controller Digital Design Engineer

This Jobot Job is hosted by: Karyn SpiesAre you a fit? Easy Apply now by clicking the "Apply Now" buttonand sending us your resume.Salary: $150,000 - $225,000 per yearA bit about us:Leading IC design company dedicated to providing high-performance, low-power IC solutions for cloud computing and data center markets. These products are designed for a variety of memory modules to enable high-speed, large-capacity, high-reliability and low-power memory solutions for high-performance computing.This is a fantastic opportunity to join a successful and growing organization with an amazing culture. Interested in learning more? Apply today!Why join us?Hybrid work scheduleAnnual bonusStock planCompetitive compensationFull suite of benefitsRelocation assistance and/or sponsorship as neededJob DetailsWe are looking for a Principal Digital Design Engineer with over 15 years of experience who will help architect and develop RTL for various products with the area of focus being DDR server-class memory controllers. The ideal candidate will have RTL to GDSII flow experience using industry standard tools. In addition, knowledge of embedded micro-controllers such as RISCV and I2C/I3C protocols are advantageous. You will work with other global team members in designing both building blocks for the various products, as well as designing the entire new product for the company.Responsibilities:Mentor and lead cross-functional teams to architect, develop and debug digital and mixed signal circuitsDesign various logic & state machines in System Verilog/Verilog RTLDevelop and debug RTL, using industry-standard simulation and synthesis tools, along with LEC, CDC, Lint, DFT and STA toolsProvide PPA (Power, Performance, Area) and schedule estimates, as well as design specifications for the RTLCoordinate with Verification/AMS design teams to ensure proper operation and functional and code coverageProvide floor-planning and support integration of digital & analog circuits at top levelWork in cooperation with the methodology and CAD teamsJob Qualifications:BS or MS in Electrical Engineering, Computer Engineering or equivalentMust have 15 years of industry experience with deep understanding in the architecture definition of DDR4/5 server-class memory controllersFamiliarity with ECC (SECDEC) and CRCKnowledge of JEDEC memory standards and CHI/AXI interconnect and bus protocolsExperience in high speed and low power digital design in advanced deep sub-micron processesUnderstand how to obtain minimum latency and maximum bandwidthUnderstand the tradeoff with command placement and scheduling, can efficiently manage activate and pre-charge commandsProficient with System Verilog/Verilog RTL for both behavioral simulations and synthesisProficient with Design Compiler and PrimeTimeProgramming/scripting know-how, e.g. Perl, Tcl and/or PythonExperience with LinuxExperience with embedded micro-controllers is beneficialInterested in hearing more? Easy Apply now by clicking the "Apply Now" button.

Created: 2024-11-07